1. Field
The disclosure relates to a semiconductor device and a semiconductor device module, and in particular, it relates to a semiconductor device and a semiconductor device module enabling more accurate testing of a connection state of the internal wiring in a semiconductor module in which a plurality of semiconductor devices are mounted, and between the semiconductor devices mounted in the semiconductor device module.
2. Description of Related Art
FIG. 9 is a block circuit diagram showing a configuration of a semiconductor device according to Japanese Laid-open Patent Publication No. 2004-247523. In FIG. 9, 101 denotes a semiconductor chip that will serve as a base (hereinafter referred to as master chip), 102 denotes an internal circuit integrated in the master chip 101, 115 denotes a semiconductor chip stacked on the master chip 101 (hereinafter referred to as slave chip), 116 denotes an internal circuit integrated in the slave chip 115, 117 through 120 denote inter-chip connection terminals that deliver signals between the internal circuit 116 and the internal circuit 102 provided on the master chip 101, 121 through 124 denote diodes connected to the inter-chip connection terminals 117 through 120, 125 through 128 denote inter-chip connection terminals that deliver signals between the internal circuit 102 provided on the master chip 101 and the internal circuit 116 provided on the slave chip 115, and 133 through 136 denote wires that connect the inter-chip connection terminals 117 through 120 with the inter-chip connection terminals 125 through 128. Switch elements 201 through 204 are respectively connected in series between the inter-chip connection terminals 125 through 128 and the conductivity test terminal 137a. A switch control section 200 controls the switch elements 201 through 204 so that one switch element at a time becomes conductive at the time of conductivity testing. Line switch elements 205 through 208 are respectively connected in series between the inter-chip connection terminals 125 through 128 and the diodes 129 through 132.
Next, a description will be given on the operation of the semiconductor device of Japanese Laid-open Patent Publication No. 2004-347523 having the configuration described above. A conductivity test terminal 138a sets in advance the line switch elements 205 through 208 to a non-conductive state, thereby blocking the current pathway to diodes 129 through 132. When testing the conductivity of wire 133, the switch control section 200 controls switch 201 alone to become conductive and controls switches 202 through 204 to become non-conductive. The switch control section 200 then applies a potential exceeding a (power source potential (VDD)+a threshold voltage Vt of diode 121) with respect to conductivity test terminal 137a and simultaneously measures the current flowing to the conductivity test terminal 137a. Here, in a normal state in which the wire 133 is not faulty, a current flows in a forward direction with respect to the power source potential (VDD), to the diode 121, so that a determination can be made that wire 133 is conductive. On the other hand, if the current value is 0, it is detected that wire 133 is disconnected. Disconnections in all wires 133 through 136 can be detected by applying the above sequence in turn to each one terminal from all inter-chip connection terminals 125 through 128.
Here, switch elements 201 through 208 are generally provided with a PMOS transistor. However, in the circuit of the Japanese Patent Application Publication No. 2004-347523 shown in FIG. 9, a potential exceeding (a power source potential (VDD)+threshold voltage Vt of the diode 121) is applied to the conductivity test terminal 137a. Thus, since a power source potential VDD is generally employed in the PMOS transistor as a substrate bias potential, a PN junction leak current leaking from the source to the substrate is generated. As a result, a leak current is generated in switch elements 201 through 208 which thus obstructs normal performance of open circuit failure testing. Japanese Laid-open Patent Publication No. 2004-347523 includes no description of a specific method to solve the above problem.